Standard cell layout with regular contact placement,” Semiconductor Manufacturing

Abstract—The practicability and methodology of applying regularly placed contacts on layout design of standard cells are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows for a reduction of critical dimensions. Although placing contacts on a grid adds restrictions during cell layout, overall circuit area can be made smaller by a careful selection of the grid pitch, allowing slight contact offset, applying double exposure, and shrinking the minimum size and pitch. The contact level of 250 nm standard cells was shrunk by 10%, resulting in an area change ranging from 20 % to +25 % with an average decrease of 5 % for the 84 cells studied. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4 % and 2%, respectively. Index Terms—Double exposure, fabrication-friendly layout, low 1 lithography, regularly placed contact, RETs, standard cells